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xr-t5683a ...the analog plus company tm pcm line interface chip rev. 2.01 1995 exar corporation, 48720 kato road, fremont, ca 94538 (510) 668-7000 fax (510) 668-7017 1 june 1997-3 features single 5v supply receiver input can be either balanced or unbalanced up to 8.448mbps operation in both tx and rx directions ttl compatible interface device can be used as a line interface unit with- out clock recovery applications t1, t2, e1 & e2 rates, pcm line interface network multiplexing and terminating equipment general description the xr-t5683a is a pcm line interface chip consisting of both transmit and receive circuitry. this device is offered in a plastic dual in-line (pdip) or in a surface mount package (soic). the maximum bit rate of the chip is 8.448mbps, and the signal level to the receiver can be attenuated by -10db cable loss at one-half the bit rate. at nominal supply voltage operation, the typical current consumption is 40ma. ordering information part no. package operating temperature range xr-t5683aip 18 lead 300 mil pdip -40 c to +85 c XR-T5683AID 18 lead 300 mil jedec soic -40 c to +85 c block diagram figure 1. block diagram rpos 11 positive threshold comparator pdc 1 peak detector bias rxdata+ 2 rxdata- 3 negative threshold comparator te 4 ttlbuffer tank bias 6 rneg 10 rclk 8 bias 5 txdata+ 13 open collector driver bias tv cc 18 rgnd 7 rv cc 9 tpos 17 tclk 16 tneg 12 tgnd 14 txdata- 15 open collector driver ttlbuffer ttlbuffer
xr-t5683a 2 rev. 2.01 pin configuration 18 lead pdip (0.300o) 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 tv cc tpos tclk txdata- pdc rxdata+ rxdata- te tgnd txdata+ tneg rpos bias tank bias rgnd rclk rneg rv cc 18 lead soic (jedec, 0.300o) 18 1 10 9 2 3 4 5 6 7 15 14 13 12 11 17 16 8 pdc rxdata+ rxdata- te bias tank bias rgnd rclk rv cc tv cc tpos tclk txdata- tgnd txdata+ tneg rpos rneg pin description pin # symbol type description 1 pdc peak detector capacitor. this pin should be connected to a 0.1 m f capacitor. 2 rxdata+ i receive analog input positive. line analog input. 3 rxdata- i receive analog input negative. line analog input. 4 te o tank excitation output. this output connects to one side of the tank circuitry. 5 bias o bias. this output is to be connected to the center tap of the receive transformer. 6 tank bias o tank bias. the tank circuitry is biased via this output. 7 rgnd receiver ground. to minimize ground interference a separate pin is used to ground the receive section. 8 rclk o recovered receive clock. recovered clock signal to the terminal equipment. 9 rv cc receive supply voltage. 5v supply voltage to the receive section. 10 rneg o receive negative data. negative pulse data output to the terminal equipment (active low). 11 rpos o receive positive data. positive pulse data output to the terminal equipment (active low). 12 tneg i transmit negative data. tneg is valid while tclk is high. 13 txdata+ o transmit positive output. transmit bipolar signal is driven to the line via a transformer. 14 tgnd transmit ground. 15 txdata- o transmit negative output. transmit bipolar signal is driven to the line via a transformer. 16 tclk i transmit clock. timing element for tpos and tneg. 17 tpos i transmit positive data. tpos is valid while tclk is high. 18 tv cc transmit supply voltage. 5v supply voltage to the transmit section.
xr-t5683a 3 rev. 2.01 electrical characteristics test conditions: v cc = 5.0v 5% , t a = 25 c , unless otherwise specified. parameters min. typ. max. unit conditions dc electrical characteristics supply voltage 4.75 5 5.25 v supply current 40 55 ma total current to pin 9 & pin 18 transmitter outputs open receiver section tank drive current 300 500 700 m a measured at pin 4, v cc = 5v clock output low 0.3 0.6 v measured at pin 8, i ol = 1.6ma clock output high 3.0 3.6 v measured at pin 8, i oh = -400 m a data output low 0.3 0.6 v measured at pin 10 & 11, i ol = 1.6ma data output high 3.0 3.6 v measured at pin 10 & 11, i oh = -400 m a transmitter section driver output low 0.6 0.8 1.0 v measured at pin 13 & 15, i ol = 40ma output leakage current 0 100 m a measured in off state, output pull-up to + 20v input high voltage 2.2 v cc v measured at pin 12, 16 & 17, i ol = 40ma, v ol = 1.0v input low voltage 0.8 v measured at pin 12, 16 & 17, output off input low current -1.6 ma measured at pin 12, 16 & 17, input low voltage = 0. 4v input high current 40 m a measured at pin 12, 16 & 17, input high voltage = 2.7v output low current 40 ma measured at pin 13 & 15, v ol = 1.0v ac electrical characteristics receiver section input level 6 6.6 vpp measured between pin 2 & 3 loss input signal alarm level 1.6 vpp measured between pin 2 & 3, alarm on pull data output high input impedance at 8,448mhz 2.5 k w measured between pin 2 & 3, with sinewave input clock duty cycle 35 50 65 % measured at pin 8 at 2.0v clock rise & fall time 20 ns measured at pin 8, c l = 15pf data pulse width 35 50 75 % of clock period measured at pin 10 & 11, at 1v dc level, cable loss = 0 notes bold face parameters are covered by production test and guaranteed over operating temperature range.
xr-t5683a 4 rev. 2.01 electrical characteristics (cont'd) parameters min. typ. max. unit conditions ac electrical characteristics (cont'd) transmitter section pulse width at 8.448mhz 53 65 ns measured at pin 13 & 15, see figure 6 output rise time 12 25 ns see figure 5 output fall time 12 25 ns see figure 5 output pulse imbalance 2.5 ns at 50% output level specifications are subject to change without notice notes bold face parameters are covered by production test and guaranteed over operating temperature range. absolute maximum ratings supply voltage +20v . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature -65 c to +150 c . . . . . . . . . . . . . . system description the incoming bipolar pcm signal which is attenuated and distorted by the cable is applied to the threshold comparator and the peak detector. the peak detector generates a dc reference for the threshold comparator for data and clock extraction. an external tank circuit tuned to the appropriate frequency is added for the later operation. the clock signal, data (+) and data (-) all go through a similar level shifter to be converted into ttl level to be compatible for digital processing. in the transmit direction, the output drivers consist of two identical ttl inputs with open collector output stages. the maximum low level current these output stages can sink is 40ma. with full width data (nrz) applied to the inputs together with a synchronized clock, the output will generate a bipolar signal when driving a center-tapped transformer. a block diagram of the xr-t5683a is shown in figure 1 . the clock recovery uses an external tank circuit. the receive data will create an excitation for the tank circuitry which in turn will create a recovered, received clock (rclk).
xr-t5683a 5 rev. 2.01 table 1 shows typical expected jitter tolerance. the following measurements have been done at a transmission rate of t1 (1.544mhz). (see figure 2 ). jitter 1.544mbs in ui jitter 1.544mbs in ui 10hz >10ui 5khz 1.3ui 100hz >10ui 8khz 0.8ui 500hz >10ui 10khz 0.7ui 1khz 6.5ui 32khz 0.5ui 2khz 3.3ui 50khz 0.45ui 3khz 2.1ui 77khz 0.45ui 4khz 1.5ui - - v cc = +5v 5%, t a = 25 c table 1. jitter tolerance at 1.544mbps with 6db cable loss tpos rpos 6db cable attenuation pattern generator hp3781b clock rxdata- rxdata+ xr-t5683a rx rclk rneg xr-t5683a tx tclk tneg generator hp3785b jitter txdata+ txdata- figure 2. jitter measurement set-up (transmitter side) clock phase shift circuit jitter analyzer hp3785b (receive side)
xr-t5683a 6 rev. 2.01 rxdata+ rclk output at pin 8 rpos output at pin 11 rneg output at pin 10 figure 3. receiver timing diagram with 1-1-1-1-1-1 pattern tclk clock to pin 16 tpos to pin 17 bipolar signal at transformer output tneg to pin 12 figure 4. transmitter input timing diagram
xr-t5683a 7 rev. 2.01 notes 1 inputs that are not connected to pulse generator will be tied to v cc via 1k resistor. 2 c1 includes probe and jig capacitance. figure 5. test circuit 100 0.1 m f v cc = 5v output ci=15pf 2 0v pin 9 & 18 pin 13 & 15 0v pin 7 & 14 8.448mhz pulse generator input xr-t5683a pin 12,16,17 1 figure 6. transmitter test circuit and switching waveforms (measured at 8.448mbps) 3v 90% 59ns <5ns 90% input pulse from generator 10% 1.5v output from pin 13 or pin 15 90% 1.5v 10% 15ns typ. 15ns typ. 90% 50% 50% 10% 10% 0v +5v vol pulse width rise time fall time <5ns
xr-t5683a 8 rev. 2.01 v cc tip ring t1 pe65415 1:1:1 0.1 m f 390 w rxdata+ 2 rxdata- 3 bias 5 te 4 tank bias 6 rv cc 9 rgnd 7 rclk 8 pdc 1 tv cc 18 txdata+ 13 txdata- 15 tgnd 14 rneg 10 rpos 11 tneg 12 tpos 17 tclk 16 u1 xr-t5683a 56 w tip t2 pe65415 1:1:1 ring 56 w r c l 0.1 m f 0.1 m f rneg rpos tneg tpos tclk v cc 0.1 m f 0.1 m f rclk figure 7. application circuit
xr-t5683a 9 rev. 2.01 input and output transformers pulse engineering types pe-65415, pe-65771 or pe-65835 transformers, may be used for both the input and output transformers. these three parts, which are all 1ct:2ct turns ratio and have similar electrical specifications, are wound on small, epoxy-encapsulated, torroid cores. they differ in physical size, operating temperature range and voltage isolation. these transformers are suitable for operation over the 1.544 through 8.448mbps range which includes t1, t2, e1 and e2. schott-part number nominal inductance mechanical style bit rate (mbit/s) tuning cap. (see note) 24443 48 m hy with ct rm 5 core, 4 pin bobbin 1.544(t1) 200pf 4 pi n b o bbi n 2.048(e1) 100pf 24444 5 m hy with ct 14 x 8 potcore, 6 pin bobbin 6.312(t2) 100pf 6 pi n b o bbi n 6.448(e2) 60pf table 2. inductor selection notes - capacitor values shown combined with typical stray capacitance will normally resonate the tank circuit at the specific bit ra te. - the center-tapped inductor (l) eliminates clock amplifier overload by reducing the signal amplitude applied to t5683a pin 4. while feeding pseudo-random data into the receive input, tune this inductor for minimum jitter on the recovered clock (pin 8) as view ed on an oscilloscope. - r, which may be in the 20k to 50k w range, is optional and may be used to lower clock recovery circuit q if desired. magnetic supplier information: pulse telecom product group p.o. box 12235 san diego, ca 92112 tel. (619) 674-8100 fax. (619) 674-8262 john marshall schott corporation 1838 elm hill pike, suite 100 nashville, tn 37210 tel. (615) 889-8800 fax (615) 885-0834
xr-t5683a 10 rev. 2.01 18 lead plastic dual-in-line (300 mil pdip) rev. 1.00 18 1 10 9 d eb 1 a 1 e 1 c e a 2 l b seating plane symbol min max min max inches a 0.145 0.210 3.68 5.33 a 1 0.015 0.070 0.38 1.78 a2 0.115 0.195 2.92 4.95 b 0.014 0.024 0.36 0.56 b 1 0.030 0.070 0.76 1.78 c 0.008 0.014 0.20 0.38 d 0.845 0.925 21.46 23.50 e 0.300 0.325 7.62 8.26 e 1 0.240 0.280 6.10 7.11 e 0.100 bsc 2.54 bsc e a 0.300 bsc 7.62 bsc e b 0.310 0.430 7.87 10.92 l 0.115 0.160 2.92 4.06 a 0 15 0 15 millimeters a a note: the control dimension is the inch column e b e a
xr-t5683a 11 rev. 2.01 symbol min max min max a 0.093 0.104 2.35 2.65 a 1 0.004 0.012 0.10 0.30 b 0.013 0.020 0.33 0.51 c 0.009 0.013 0.23 0.32 d 0.447 0.463 11.35 11.75 e 0.291 0.299 7.40 7.60 e 0.050 bsc 1.27 bsc h 0.394 0.419 10.00 10.65 l 0.016 0.050 0.40 1.27 a 0 8 0 8 inches millimeters 18 lead small outline (300 mil jedec soic) rev. 1.00 e 18 10 9 d e h b a l c a 1 seating plane a note: the control dimension is the millimeter column 1
xr-t5683a 12 rev. 2.01 notice exar corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein are only for illustration purposes and may vary depending upon a user's specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circum- stances. copyright 1995 exar corporation datasheet june 1997 reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

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